In many modern applications, an electronic system is made of multiple of subsystems. These subsystems could be blocks, modules or discrete chips. For successful operation, one of the key tasks is the data communication among the subsystems. Data communication refers to the work of transferring information from one subsystem to one (or more) other subsystem(s). The information sender is often termed transmitter and the information taker is called receiver. The information transfer can be carried out in either digital or analog fashion. In most modern systems, digital data communication is the preferred method due to its low cost, high data rate and high reliability.
FIG. 1 shows the structure of a typical transmitter and receiver system where a sequence of digital data is to be transferred from the transmitter to the receiver. Transmitter subsystem 110 has a signal processing & transmitter circuit 111 and a clock generation circuit 112. Circuit 111 is used to generate the signal data that needs to be transferred. It also has a transmitter circuit that outputs the data to the transmission channel. Circuit 111 is operated under the control of a clock signal clk_t which is generated from circuit 112. Usually, the data is sent to the channel at the same rate of clk_t. At the receiver side, subsystem 120 has a receiver & signal processing circuit 121. It also has its own clock generation circuit 122 that produces a clock signal clk_r. Circuit 121 is operated under the control of clk_r.
Between the transmitter and the receiver, there are two electrical channels for carrying out the communication task. WIRE_D 130 is used for data and WIRE_C 140 is for clock. Since both the data and clock signals are sent from the transmitter, the receiver can simply use the received clock signal to latch the received data. The major advantage of this scheme is that the receiver is always operated at the same, or in a fixed proportional, rate of that of the transmitter. Thus, it significantly reduces the possibility of data loss.
However, there are a few drawbacks with this scheme. The first one is the high cost. As shown, to transfer one sequence of digital data, two electrical paths are required. This fact not only increases the manufacture cost but also demands larger physical area in the system to accommodate all the paths. In some applications, there could be tens or hundreds of transmitter-receiver pairs in the system. In those cases, the two-paths-solution requires large amount of resource to fabricate the system. Further, the physical layout of these many paths can cause route congestion problem if the physical size of the system is not large enough.
The second problem is the skew between the data and clock signals when they arrive at the receiver. Mostly likely, the data and clock will arrive at their destinations at different times since they are transferred in different electrical paths with different time delays. This time difference is called skew. The amount of skew is hard to be predicted in the chip design time since it will be largely affected by the PCB board design and many other factors. The amount of skew can take large portion of the bit time. This can cause the receiver to make error when latching the data since the received clock is not aligned properly with the received data. The higher the clock rate (the shorter the bit time) is, the severer the problem will be. When multiple data paths are accompanied by one clock path, this scheme becomes almost impossible to use since different data paths experience different delays and it is difficult for the clock generation circuit in the receiver to decide which data path is the target for delay (or phase) optimization.
This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.